Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs-Reference-Cited by-同舟云学术

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Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs

Published:2015-04 Issue:4 Volume:34 Page:540-553
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Panth Shreepad,Samadi Kambiz,Du Yang,Lim Sung Kyu

Funder

Qualcomm Research

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/7061937/07001641.pdf?arnumber=7001641

Cited by 43 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Timing-Aware Tier Partitioning for 3D ICs with Critical Path Consideration;2024 International Conference on Electronics, Information, and Communication (ICEIC);2024-01-28

2. CoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICs;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

3. Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing;ACM Transactions on Design Automation of Electronic Systems;2023-12-18

4. Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

5. Impact of gate-level clustering on automated system partitioning of 3D-ICs;Microelectronics Journal;2023-09

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