Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs-Reference-Cited by-同舟云学术

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Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs

Published:2023-11 Issue:11 Volume:42 Page:4296-4309
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Hung Shao-Chun¹^ORCID,Banerjee Sanmitra²,Chaudhuri Arjun²^ORCID,Kim Jinwoo³^ORCID,Lim Sung Kyu³,Chakrabarty Krishnendu⁴^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA

2. NVIDIA Corporation, Santa Clara, CA, USA

3. School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA

4. School of Electrical Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA

Funder

National Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

https://ieeexplore.ieee.org/ielam/43/10288105/10123099-aam.pdf

Reference39 articles.

1. NodeRank: Observation-Point Insertion for Fault Localization in Monolithic 3D ICs∗

2. Principal component analysis

3. An Interlayer Interconnect BIST and Diagnosis Solution for Monolithic 3-D ICs

4. Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs

5. SPRING: A Sparsity-Aware Reduced-Precision Monolithic 3D CNN Accelerator Architecture for Training and Inference

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