A Library for Combinational Circuit Verification Using the HOL Theorem Prover-Reference-Cited by-同舟云学术

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A Library for Combinational Circuit Verification Using the HOL Theorem Prover

Published:2018-02 Issue:2 Volume:37 Page:512-516
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Shiraz Sumayya,Hasan Osman^ORCID

Funder

National Research Program for Universities of Higher Education Commission, Pakistan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/8263325/07930505.pdf?arnumber=7930505

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Formal timing analysis of gate-level digital circuits using model checking;Microprocessors and Microsystems;2024-09

2. HVoC: a Hybrid Model Checking - Interactive Theorem Proving Approach for Functional Verification of Digital Circuits;Journal of Electronic Testing;2021-06-26

3. Research on Automation Strategy of Coq;Advances in Artificial Intelligence and Security;2021

4. Design and Formal Analysis of an Authentication Protocol, eWMDP on Wearable Devices;IEEE Access;2019

5. Formal Timing Analysis of Digital Circuits;Communications in Computer and Information Science;2019

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