SRAM With Buried Power Distribution to Improve Write Margin and Performance in Advanced Technology Nodes
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/55/8771270/08731977.pdf?arnumber=8731977
Cited by 23 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
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3. A Novel Zigzag SRAM Bitcell Design in the Complementary FET Framework;IEEE Transactions on Electron Devices;2023-09
4. Invited: Buried Power Rails and Back-side Power Grids: Prospects and Challenges;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09
5. 3D SRAM Macro Design in 3D Nanofabric Process Technology;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07
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