Invited: Buried Power Rails and Back-side Power Grids: Prospects and Challenges
Author:
Affiliation:
1. The University of Texas at Austin,Circuit Research Lab,Chandra Department of Electrical and Computer Engineering,Austin,TX,USA,78712
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10247654/10247655/10247775.pdf?arnumber=10247775
Reference21 articles.
1. Buried Power SRAM DTCO and System-Level Benchmarking in N3
2. SRAM With Buried Power Distribution to Improve Write Margin and Performance in Advanced Technology Nodes
3. Buried Interconnects for Sub-5 nm SRAM Design
4. Buried Bitline for sub-5nm SRAM Design
5. A Systematic Evaluation of EM and Power Side-Channel Analysis Attacks on AES Implementations
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1. Thermal Mitigation Strategy for Backside Power Delivery Network;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28
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