A Combined N/PFET CFET-Based Design and Logic Technology Framework for CMOS Applications-Reference-Cited by-同舟云学术

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A Combined N/PFET CFET-Based Design and Logic Technology Framework for CMOS Applications

Published:2023-12 Issue:12 Volume:42 Page:4999-5005
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Zhu Xiaona¹^ORCID,Ding Rongzheng¹^ORCID,Tao Ouwen²^ORCID,Zhao Yage¹,Tang Peishun¹,Zhang David Wei¹,Lu Ye³^ORCID,Yu Shaofeng¹^ORCID

Affiliation:

1. School of Microelectronics, Fudan University, Shanghai, China

2. State Key Laboratory of ASIC and System, School of Information Science and Technology, Fudan University, Shanghai, China

3. State Key Laboratory of ASIC and System, School of Information Science and Technology, and the Zhangjiang Fudan International Innovation Center, Fudan University, Shanghai, China

Funder

Innovation Program of Shanghai Municipal Education Commission

Shanghai Pujiang Program

Natural Science Foundation of Shanghai

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/10325328/10143298.pdf?arnumber=10143298

Reference16 articles.

1. Transistor Compact Model Based on Multigradient Neural Network and Its Application in SPICE Circuit Simulations for Gate-All-Around Si Cold Source FETs

2. MOS transistor modelling using neural network

3. BSIM-CMG: Standard FinFET compact model for advanced circuit design

4. Artificial Neural Network-Based Compact Modeling Methodology for Advanced Transistors

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