Design Space Exploration of TRNG Latches for Improved Entropy and Efficiency
Author:
Affiliation:
1. Ohio State University,Department of Electrical and Computer Engineering,Columbus,Ohio
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10161731/10161695/10161842.pdf?arnumber=10161842
Reference6 articles.
1. Trends in Hardware Security: From Basics to ASICs
2. True Random Number Generator With a Metastability-Based Quality Control
3. On the Excess Noise Factors and Noise Parameter Equations for RF CMOS
4. An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch
5. An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 0.012‐mm2 0.244‐pJ/bit successive approximation register analog‐to‐digital converter‐based true random number generator for Internet of Things applications in a 65‐nm complementary metal–oxide–semiconductor;International Journal of Circuit Theory and Applications;2024-05-21
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