A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3× Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI-Reference-Cited by-同舟云学术

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3× Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

Published:2023 Issue: Volume:6 Page:13-16
ISSN:2573-9603
Container-title:IEEE Solid-State Circuits Letters
language:
Short-container-title:IEEE Solid-State Circuits Lett.

Author:

Yigit Andac¹^ORCID,Casarrubias Emmanuel Nieto¹,Giterman Robert¹^ORCID,Burg Andreas¹^ORCID

Affiliation:

1. Institute of Electrical Engineering, EPFL, Lausanne, Switzerland

Funder

BRIDGE Project

Innosuisse Project

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8011414/10016898/10002939.pdf?arnumber=10002939

Reference12 articles.

1. A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications

2. A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches

3. A word-line boost driver design for low operating voltage 6T-SRAMs

4. A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET

5. Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM;kulkarni;Proc IEEE Int Solid-State Circuits Conf,2012

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