A word-line boost driver design for low operating voltage 6T-SRAMs
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/6276898/6291930/06291950.pdf?arnumber=6291950
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Error reduction of SRAM-based physically unclonable function for chip authentication;International Journal of Information Security;2023-02-20
2. A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3× Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI;IEEE Solid-State Circuits Letters;2023
3. A 350 mV, 2 MHz, 16-kb SRAM with programmable wordline boosting in the 65 nm CMOS technology;Analog Integrated Circuits and Signal Processing;2021-07-12
4. An error detecting scheme with input offset regulation for enhancing reliability of ultralow-voltage SRAM;Microelectronics Reliability;2020-11
5. A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28-nm FD–SOI;IEEE Transactions on Circuits and Systems I: Regular Papers;2018-04
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