A 350 mV, 2 MHz, 16-kb SRAM with programmable wordline boosting in the 65 nm CMOS technology
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s10470-021-01907-x.pdf
Reference35 articles.
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3. Calhoun, B., Wang, A., & Chandrakasan, A. (2005). Modeling and sizing for minimum energy operation in subthreshold circuits. IEEE Journal of Solid-State Circuits, 40(9), 1778–1786.
4. Calhoun, B.H., & Chandrakasan, A. (2004). Characterizing and modeling minimum energy operation for subthreshold circuits. In Proceedings of the 2004 international symposium on low power electronics and design—ISLPED ’04 (pp. 90–95).
5. Chiu, Y. W., Hu, Y. H., Tu, M. H., Zhao, J. K., Chu, Y. H., Jou, S. J., & Chuang, C. T. (2014). 40 nm bit-interleaving 12T subthreshold SRAM with data-aware write-assist. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(9), 2578–2585.
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