A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit
Author:
Funder
Ministry of Science and Technology, Taiwan
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9624469/09592684.pdf?arnumber=9592684
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology;International Journal of Circuit Theory and Applications;2024-06-27
2. A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS Process;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19
3. A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-10
4. Schmitt-Trigger-Based Low Power SRAM Implemented Using 45-nm CMOS Technology;2023 IEEE Region 10 Symposium (TENSYMP);2023-09-06
5. A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process;IET Circuits, Devices & Systems;2023-01-10
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