A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS Process-Reference-Cited by-同舟云学术

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A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS Process

Published:2023-11-19 Issue: Volume: Page:50-54
ISSN:
Container-title:2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
language:
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Author:

Sangalang Ralph Gerard B.¹,Chen Wei-Zhen¹,Wang Chua-Chin¹

Affiliation:

1. National Sun Yat-Sen University,Department of Electrical Engineering,Kaohsiung,Taiwan,80424

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10509846/10509868/10509947.pdf?arnumber=10509947

Reference16 articles.

1. A review of emerging industry 4.0 technologies in remanufacturing

2. The fourth industrial revolution: what it means, how to respond;Schwab,2016

3. A Comprehensive Review of Energy Efficient Content Addressable Memory Circuits for Network Applications

4. A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit

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