A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process-Reference-Cited by-同舟云学术

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A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process

Published:2023-10 Issue:10 Volume:70 Page:3862-3866
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Sangalang Ralph Gerard B.¹^ORCID,Reddy Shiva¹,Tolentino Lean Karlo S.¹^ORCID,Shen You-Wei¹,Jose Oliver Lexter July A.¹,Wang Chua-Chin²^ORCID

Affiliation:

1. Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan

2. Department of Electrical Engineering and Institute of Undersea Technology, National Sun Yat-Sen University, Kaohsiung, Taiwan

Funder

National Science and Technology Council, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10262390/10164648.pdf?arnumber=10164648

Reference18 articles.

1. Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process

2. Design and Analysis of Schmitt Trigger Based 10T SRAM in 32 nm Technology

3. Schmitt Trigger based SRAM Cell for Ultralow Power Operation- A CNFET based Approach

4. Schmitt trigger-based single-ended 7T SRAM cell for Internet of Things (IoT) applications

5. One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation

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