Affiliation:
1. Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, Republic of Korea
Abstract
Individualized treatment of chronic diseases opens up great opportunities for implantable biosensor systems capable of tracking vital signals over long periods of time. To this end, low-power techniques in standby mode and the efficient utilization of storage space will be important issues for the implementation of such rechargeable implants with a built-in memory. This paper presents key circuit techniques, including a leakage-current-based clock generator that eliminates the need for an internal reference clock source, a low-standby-power 8Kbit SRAM with negative wordline and dynamic supply voltage scaling, and an adaptive sensing scheme to improve storage space utilization. When implemented with commercial 180 nm CMOS technology for the circuit simulation, approximately 70% (100 nW) of power dissipation was reduced from internal clock source, about 70% of power consumed by 8Kbit SRAM was saved, and the storage space utilization was improved by about 42.8%. In the end, the proposed implantable biosensor SoC consumes about 82.5 nW of standby power, saving about 42% from the previous approach and can last for 2.5 days using a 5 uAh thin-film battery (CYMBET® 1.7 × 2.2 mm2).
Funder
Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
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