Minimum Power Test Pattern Generator for Testing VLSI Circuits-Reference-Cited by-同舟云学术

Minimum Power Test Pattern Generator for Testing VLSI Circuits

Published:2022-04-21 Issue: Volume: Page:
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Container-title:2022 6th International Conference on Devices, Circuits and Systems (ICDCS)
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Author:

Govindaraj V.¹,Manoharan K.²,Prabha K. Lakshmi³,Dhanasekar S.⁴,Sreekanth K⁵

Affiliation:

1. Dr.N.G.P Institute of Technology,Department of ECE,Coimbatore,India

2. Sri Eshwar College of Engineering,Department of ECE,Coimbatore,India

3. SNS College of Technology,Department of Biomedical Engineering,Coimbatore,India

4. Simulus Automation Pvt Ltd,ASIC Design and Verification Engineer,Chennai,India

5. PSG Polytechnic College,Department of ECE,Coimbatore,India

Publisher

IEEE

Link

Reference24 articles.

3. Investigation on test pattern Generation and test power reduction Techniques for multiple stuck at faults;anita,0

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