Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits-Reference-Cited by-同舟云学术

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Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits

Published:2010-02 Issue:2 Volume:29 Page:313-318
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Chen Jwu-E.,Luo Pei-Wen,Wey Chin-Long

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/5395722/05395737.pdf?arnumber=5395737

Cited by 27 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Transition Point Estimation Using RC-Filtered Square Wave for Calibration of SAR ADC;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-05

2. On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC;Proceedings of the 28th Asia and South Pacific Design Automation Conference;2023-01-16

3. A Metric of Elements Placement Properties for Nonlinearity Reduction Prediction in Binary DACs;2022 Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus);2022-01-25

4. Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead;2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC);2022-01-17

5. Deterministic Dithering-Based 12-b 8-MS/s SAR ADC in 0.18-μm CMOS;IEEE Solid-State Circuits Letters;2022

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