On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC

Author:

Chiang Cheng-Yu1,Hu Chia-Lin1,Lin Mark Po-Hung1,Chung Yu-Szu1,Jou Shyh-Jye1,Wu Jieh-Tsorng1,Chiang Shiuh-hua Wood2,Liu Chien-Nan Jimmy1,Chen Hung-Ming1

Affiliation:

1. National Yang Ming Chiao Tung University, Hsinchu, Taiwan

2. Brigham Young University

Publisher

ACM

Reference19 articles.

1. Avishek Biswas and Anantha P. Chandrakasan . 2018. Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications . In 2018 IEEE International Solid-State Circuits Conference (ISSCC). pp. 488 -- 490 . Avishek Biswas and Anantha P. Chandrakasan. 2018. Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications. In 2018 IEEE International Solid-State Circuits Conference (ISSCC). pp. 488--490.

2. Hung-Ming Chen , Chia-Lin Hu , Kang-Yu Chang , Alexandra Küster , Yu-Hsien Lin , Po-Shen Kuo , Wei-Tung Chao , Bo-Cheng Lai , Chien-Nan Liu , and Shyh-Jye Jou . 2020 . On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. In 2020 IEEE/ACM International Conference on Computer Aided Design (ICCAD). pp. 1 -- 8 . Hung-Ming Chen, Chia-Lin Hu, Kang-Yu Chang, Alexandra Küster, Yu-Hsien Lin, Po-Shen Kuo, Wei-Tung Chao, Bo-Cheng Lai, Chien-Nan Liu, and Shyh-Jye Jou. 2020. On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. In 2020 IEEE/ACM International Conference on Computer Aided Design (ICCAD). pp. 1--8.

3. Jwu- E. Chen , Pei-Wen Luo , and Chin-Long Wey . 2010. Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) ( 2010 ), pp. 313 -- 318 . Jwu-E. Chen, Pei-Wen Luo, and Chin-Long Wey. 2010. Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (2010), pp. 313--318.

4. Jan Craninckx and Geert Van der Plas . 2007 . A 65fJ/conversion-step 0-to-50MS/s 0-to-0.7 mW 9b charge-sharing SAR ADC in 90nm digital CMOS . In 2007 IEEE International Solid-State Circuits Conference (ISSCC). pp. 246 -- 600 . Jan Craninckx and Geert Van der Plas. 2007. A 65fJ/conversion-step 0-to-50MS/s 0-to-0.7 mW 9b charge-sharing SAR ADC in 90nm digital CMOS. In 2007 IEEE International Solid-State Circuits Conference (ISSCC). pp. 246--600.

5. Husni Habal , Florin Burcea , and Helmut Graeb . 2016 . Procedural capacitor placement in differential charge-scaling converters by nonlinearity analysis . In 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC). pp. 1 -- 6 . Husni Habal, Florin Burcea, and Helmut Graeb. 2016. Procedural capacitor placement in differential charge-scaling converters by nonlinearity analysis. In 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC). pp. 1--6.

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