A Metric of Elements Placement Properties for Nonlinearity Reduction Prediction in Binary DACs
Author:
Affiliation:
1. Peter the Great St. Petersburg Polytechnic University,St. Petersburg,Russia
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9755448/9755449/09755486.pdf?arnumber=9755486
Reference24 articles.
1. Comparative Analysis of Switching Schemes for 6-bit Arrays in Binary DACs
2. A Gradient-Error and Edge-Effect Tolerant Switching Scheme for a High-Accuracy DAC
3. New sequence switching and layout technique for high-speed high-accuracy current-steering DACs
4. A 12-bit current steering DAC with 2-dimensional gradient-error tolerant switching scheme
5. Switching sequence optimization for gradient errors compensation in the current-steering DAC design
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1. Hardware Implementation of a Convolutional Neural Network;2023 International Conference on Electrical Engineering and Photonics (EExPolytech);2023-10-19
2. Comparative Analysis of Switching Schemes for 8-bit Arrays in Binary DACs;2022 International Conference on Electrical Engineering and Photonics (EExPolytech);2022-10-20
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