Switching sequence optimization for gradient errors compensation in the current-steering DAC design

Author:

Wu Kejun,Li Jing,Wang Xiangzhan,Ning Ning,Xu Kaikai,Yu Qi

Funder

Natural Science Foundation of China

Publisher

Elsevier BV

Subject

General Engineering

Reference17 articles.

1. A 240mW 16b 3.2GS/s DAC in 65nm CMOS with <-80dBc IM3 up to 600MHz;Van de Vel;in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC),2014

2. Low-overhead self-healing methodology for current matching in current-steering DAC;Liu;IEEE Trans. Circuits Syst. II: Express Briefs,2015

3. A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire nyquist bandwidth,;Lin,2013

4. A 1.8-V 12-Bit 250-MS/s 25-mW Self-calibrated DAC;Chi;in Proc. ESSCIRC,2010

5. A 14 bit 200 MS/s DAC with SFDR >78 dBc, IM3 <- 83 dBc and NSD <-163 dBm/Hz across the whole nyquist band enabled by dynamic-mismatch mapping;Tang;IEEE J. Solid State Circuits,2011

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3. A 12-Bit Current-Steering DAC With Unary- Splitting -Binary Segmented Architecture and Improved Decoding Circuit Topology;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-10

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