Design of Low-Power High-Speed 8 Bit CMOS Current Steering DAC for AI Applications

Abstract

This paper describes a current steering 8-bit DAC architecture for low power and high-speed assistance in AI networks. This design is most suitable for 5G and next-generation high-speed communication systems on chip (SoCs). This DAC keeps a constant load current and leads to faster operations in wideband portable device applications. The design is based on weighted current transmission through current mirrors wherein current reduces from MSB to LSB continuously. By choosing a low current for LSB, the power dissipation reduces. Power and area are also reduced by using a 2-bit binary to thermometer decoder. The DAC's integral nonlinearity (INL) and differential nonlinearity (DNL) are found to be within 0.4 and 0.9 LSB, respectively. The DAC's highest operating speed is 1GHz, with a power dissipation of around 24.2 mW with the supply voltage of 1.8v using 180nm CMOS technology.