A fast and simple method to place sub-die under Chip-let architecture based on thermal simulation-Reference-Cited by-同舟云学术

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A fast and simple method to place sub-die under Chip-let architecture based on thermal simulation

Published:2023-08-08 Issue: Volume: Page:1-5
ISSN:
Container-title:2023 24th International Conference on Electronic Packaging Technology (ICEPT)
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Author:

Cao Jiangcheng¹,Man Hongtao²,Wu Xiaohu³

Affiliation:

1. Shandong Inspur Artificial Intelligence Research Institute Co., Ltd,Inspur Electronic Information Industry Co., Ltd,Jinan,China

2. Shandong Inspur Artificial Intelligence Research Institute Co., Ltd,Inspur Electronic Information Industry Co., Ltd,Beijing,China

3. Shandong Institute of Advanced Technology,Jinan,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10491594/10491891/10492004.pdf?arnumber=10492004

Reference5 articles.

1. Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse

2. A Low Computational Cost and Accurate Thermal Calculation Method for Multi-hotspot IC

3. Advanced Fan-Out Package SI/PI/Thermal Performance Analysis of Novel RDL Packages

4. A Complex Integrated Circuit Structure Transformation, Modeling and Simulation Method

5. Stress and strain Analysis of LTCC substrate Module based on Microchannel

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