A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference-Reference-Cited by-同舟云学术

A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference

Published:2023-10 Issue:10 Volume:58 Page:2839-2850
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Ye Wang¹^ORCID,Wang Linfang¹^ORCID,Zhou Zhidao¹,An Junjie¹,Li Weizeng¹,Gao Hanghang¹,Li Zhi¹,Yue Jinshan¹^ORCID,Hu Hongyang¹^ORCID,Xu Xiaoxin¹^ORCID,Yang Jianguo¹^ORCID,Liu Jing¹^ORCID,Shang Dashan¹^ORCID,Zhang Feng¹^ORCID,Tian Jinghui²,Dou Chunmeng¹^ORCID,Liu Qi²^ORCID,Liu Ming²

Affiliation:

1. Laboratory of Microelectronics Devices and Integrated Technology, State Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China

2. Frontier Institute of Chip and System, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China

Funder

National Key Research and Development Program

NSFC

Strategic Priority Research Program of the Chinese Academy of Sciences

Project of Ministry of Education (MOE) Innovation Platform

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10262388/10145046.pdf?arnumber=10145046

Reference47 articles.

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3. Design Challenges and Solutions of Emerging Nonvolatile Memory for Embedded Applications

4. A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding

5. Embedded 1 Mb ReRAM in 28 nm CMOS with 0.27-to-1 V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme;chang;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2014

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