A 2T P-Channel Logic Flash Cell for Reconfigurable Interconnection in Chiplet-Based Computing-In-Memory Accelerators
Author:
Affiliation:
1. Institute of Microelectronics of the Chinese Academy of Sciences,Beijing,China
Funder
Chinese Academy of Sciences
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10557746/10557828/10558443.pdf?arnumber=10558443
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1. First draft of a report on the EDVAC
2. CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors
3. A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference
4. A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors
5. A 14nm 100Kb 2T1R Transpose RRAM with >150X resistance ratio enhancement and 27.95% reduction on energy-latency product using low-power near threshold read operation and fast data-line current stabling scheme;Wang
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