A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems-Reference-Cited by-同舟云学术

A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems

Published:2022-05 Issue:5 Volume:57 Page:1517-1526
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Toi Takashi¹^ORCID,Wadatsumi Junji¹,Kobayashi Hiroyuki¹,Shimizu Yutaka¹,Satoh Yuji¹,Morimoto Makoto¹,Ito Rui¹,Ashida Mitsuyuki¹^ORCID,Tsubouchi Yuta¹^ORCID,Nozawa Mai¹,Urakawa Go¹,Deguchi Jun²^ORCID,Fujimoto Ryuichi¹

Affiliation:

1. Kioxia Corporation, Institute of Memory Technology Research and Development, Kawasaki, Japan

2. Center for Semiconductor Research and Development, Toshiba Corporation, Kawasaki, Japan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9761850/09696301.pdf?arnumber=9696301

Reference23 articles.

1. A 13.6-16 Gb/s wireline transceiver with dicode encoding and sequence detection decoding for equalizing 24.2 dB with 2.56 pJ/bit in 65 nm CMOS;chun;Proc IEEE Custom Integr Circuits Conf (CICC),2019

2. 6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET

3. A low-power PAM4 receiver using 1/4-rate sampling decoder with adaptive variable-gain rectification

4. A 82 mW 28 Gb/s PAM-4 digital sequence decoder with built-in error correction in 28 nm FDSOI;hossain;Proc IEEE Asian Solid-State Circuits Conf (A-SSCC),2017

5. A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects

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