A low-power PAM4 receiver using 1/4-rate sampling decoder with adaptive variable-gain rectification
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/8226344/8240197/08240221.pdf?arnumber=8240221
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Dedicated 25% Duty Cycle Clock Data Recovery for 56Gb/s PAM4 Receiver with Combined FFE+DFE;2024 9th International Conference on Integrated Circuits, Design, and Verification (ICDV);2024-06-06
2. Low jitter design for quarter-rate CDR of 100Gb/s PAM4 optical receiver;IEICE Electronics Express;2022-08-10
3. Low Jitter Design for Quarter-rate CDR of 100Gb/s PAM4 Optical Receiver;IEICE ELECTRON EXPR;2022
4. A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems;IEEE Journal of Solid-State Circuits;2022-05
5. A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces;IEEE Access;2022
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