A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea
2. Samsung Electronics, Hwaseong, South Korea
Funder
Institute of Information & communications Technology Planning & Evaluation
Korea government
Development of AI-specific parallel high-speed memory interface, 50%
Development of DRAM PIM semiconductor technology for enhanced computing function for edge, 50%
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/6287639/9668973/09858044.pdf?arnumber=9858044
Reference20 articles.
1. A 22-Gb/s PAM-4 Receiver in 90-nm CMOS SOI Technology
2. A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS
3. An Inverter-Based Analog Front-End for a 56-Gb/s PAM-4 Wireline Transceiver in 16-nm CMOS
4. A 40-Gb/s 310-fJ/b Inverter-Based CMOS Optical Receiver Front-End
5. A CMOS transconductance-C filter technique for very high frequencies
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology;IEEE Transactions on Circuits and Systems II: Express Briefs;2023
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