A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/8304413/8310156/08310210.pdf?arnumber=8310210
Cited by 33 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization;IEEE Journal of Solid-State Circuits;2024-01
2. A Low-Power 40Gb/s PAM4 Transmitter with High Speed-Latch and 3-Tap FFE;2023 5th International Conference on Circuits and Systems (ICCS);2023-10-27
3. 41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology;Electronics;2023-09-16
4. Design of Low-offset and High-speed CTLE Cell based on 65 nm Process;2023 IEEE 7th Information Technology and Mechatronics Engineering Conference (ITOEC);2023-09-15
5. A PAM4 transceiver design scheme with threshold adaptive and tap adaptive;EURASIP Journal on Advances in Signal Processing;2023-06-21
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