A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS
Author:
Affiliation:
1. Institute of Microelectronics, University of Ulm, Ulm, Germany
Funder
German Research Foundation through Deutsche Forschungsgemeinschaft
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/9926114/09744725.pdf?arnumber=9744725
Cited by 16 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Inner Transfer Functions in Incremental ΔΣ ADCs;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09
2. A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
3. A 101-dB SFDR 98.5-dB DR 20-kHz BW Continuous Time Incremental Δ∑ ADC with FIR DAC and Robust Reset Timing for Sensor Interfaces;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22
4. A 99.4 dB SFDR 91.9 dB DR Continuous-Time Incremental Delta-Sigma ADC with a Noise-Shaping SAR Quantizer and a Passive Input Feedforward Stabilization Path;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21
5. An 81.5dB SNDR, 2.5 MHz Bandwidth Incremental Continuous-Time Delta-Sigma ADC in 180 nm CMOS;IEEE Solid-State Circuits Letters;2024
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