A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs
Author:
Affiliation:
1. University of Applied Sciences and Arts,Department of Integrated Circuits and Embedded Systems,Hannover,Germany
2. Leibniz University,Institute of Microelectronic Systems,Hannover,Germany
Funder
Volkswagen Foundation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10557746/10557828/10557987.pdf?arnumber=10557987
Reference15 articles.
1. A Comparative Analysis of Parallel Delta–Sigma ADC Architectures
2. On the Transfer Behaviour of Incremental Sigma Delta Converters;Bannwarth
3. A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS
4. A Calibration-Free 96.7 dB SNDR 4 MS/s CT I-SD Modulator With Single Feedback DAC
5. A 550-$\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS
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