A 101-dB SFDR 98.5-dB DR 20-kHz BW Continuous Time Incremental Δ∑ ADC with FIR DAC and Robust Reset Timing for Sensor Interfaces-Reference-Cited by-同舟云学术

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A 101-dB SFDR 98.5-dB DR 20-kHz BW Continuous Time Incremental Δ∑ ADC with FIR DAC and Robust Reset Timing for Sensor Interfaces

Published:2024-04-22 Issue: Volume: Page:1-3
ISSN:
Container-title:2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)
language:
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Author:

Wei Cheng-En¹,Wang Cheng-Wei¹,Hung Chen-Hao¹,Wang Chi-Han¹,Chou Chuan-Tai¹,Hung Duan-Sin¹,Lu Guan-Wei¹,Chen Chia-Hung¹

Affiliation:

1. National Yang Ming Chiao Tung University

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10546337/10546338/10546405.pdf?arnumber=10546405

Reference9 articles.

1. Finite-impulse-response (FIR) feedback in continuous-time delta-sigma converters

2. A Micro-Power Two-Step Incremental Analog-to-Digital Converter

3. Incremental Delta-Sigma ADCs: A Tutorial Review

4. Theory and Applications of Incremental<tex>$Delta Sigma $</tex>Converters

5. A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS

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