A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS-Reference-Cited by-同舟云学术

A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS

Published:2022-07 Issue:7 Volume:57 Page:2068-2077
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Santana Lucas Moura¹^ORCID,Martens Ewout¹^ORCID,Lagos Jorge¹^ORCID,Hershberg Benjamin¹^ORCID,Wambacq Piet¹^ORCID,Craninckx Jan¹^ORCID

Affiliation:

1. imec, Leuven, Belgium

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9809766/09756438.pdf?arnumber=9756438

Reference18 articles.

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2. A reconfigurable ?? modulator with up to 100 MHz bandwidth using flash reference shuffling;caldwell;Proc IEEE Custom Integr Circuits Conf,2013

3. A 77dB SNDR 12.5MHz Bandwidth 0–1 MASH ∑Δ ADC Based on the Pipelined-SAR Structure

4. A 66 dB SNDR 15 MHz BW SAR assisted ?? ADC in 22 nm tri-gate CMOS;lee;Proc Symp VLSI Circuits,2013

5. A 32 nm, 1.05 V, BIST enabled, 10–40 MHz, 11–9 bit, 0.13 mm2 digitized integrator MASH ?? ADC;carlton;Symp VLSI Circuits Dig Tech Papers,2011

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