A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS-Reference-Cited by-同舟云学术

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A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS

Published:2023-09-11 Issue: Volume: Page:
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Container-title:ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)
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Author:

Santana Lucas Moura¹,Martens Ewout²,Lagos Jorge²,Wambacq Piet¹,Craninckx Jan²

Affiliation:

1. Vrije Universiteit Brussel (VUB),Dept. of Electronics and Informatics (ETRO),Brussels,Belgium

2. imec,Leuven,Belgium

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10268677/10268683/10268759.pdf?arnumber=10268759

Reference10 articles.

1. 27.5 An 80MHz-BW 640MS/s Time-Interleaved Passive Noise-Shaping SAR ADC in 22nm FDSOI Process

2. 20.3 A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4th-Order Noise-Shaping SAR ADC

3. A Time-Interleaved Continuous-Time$DeltaSigma$Modulator With 20-MHz Signal Bandwidth

4. A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$98 dB THD, and 79 dB SNDR

5. The Effect of Noise Cross-Coupling on Time-Interleaved Delta-Sigma ADCs

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Resonant Time-Domain Compute-in-Memory (rTD-CiM) ADC-Less Architecture for MAC Operations;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12

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