A 10-MHz 85.1-dB SFDR 1.1-mW continuous-time Delta–sigma modulator employing calibration-free SC DAC and passive front-end low-pass filter
Author:
Funder
Research Grants Council, University Grants Committee
Publisher
Elsevier BV
Subject
General Engineering
Reference31 articles.
1. Alias rejection of continuous-time ΔΣ modulators with switched-capacitor feedback DACs;Pavan;IEEE Trans. Circuits Syst. I. Regul. Pap.,2011
2. A 5 MHz-BW 71.7-dB SNDR two-step hybrid-domain ADC in 65-nm CMOS;Yu;Microelectron. J.,2021
3. A 950 MHz clock 47.5 MHz BW 4.7 mW 67 dB SNDR discrete time delta sigma ADC leveraging ring amplification and split-source comparator based quantizer in 28 nm CMOS;Santana;IEEE J. Solid-State Circuits,2022
4. Delta-sigma modulator based compact sensor signal acquisition front-end system;Basu;Microelectron. J.,2020
5. Analysis and design of a 20-MHz bandwidth continuous-time delta-sigma modulator with time-interleaved virtual-ground-switched FIR feedback;Baluni;IEEE J. Solid-State Circuits,2021
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2. A 125–600-MHz IF 75-dB DR Partially Time-Interleaved Bandpass DSM Based on Passive N-Path Filters;IEEE Journal of Solid-State Circuits;2024
3. A 1.3-mW 73.3-dB DR 10-MHz Bandwidth CT Delta-Sigma Modulator with a Charge-Recycled SC DAC and 52.7-dB Alias Rejection;Solid State Electronics Letters;2022
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