ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration-Reference-Cited by-同舟云学术

ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration

Published:2023-01 Issue:1 Volume:58 Page:243-255
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Tu Fengbin¹^ORCID,Wang Yiqi¹^ORCID,Wu Zihan¹^ORCID,Liang Ling²^ORCID,Ding Yufei³^ORCID,Kim Bongjin²^ORCID,Liu Leibo¹^ORCID,Wei Shaojun¹^ORCID,Xie Yuan²^ORCID,Yin Shouyi¹^ORCID

Affiliation:

1. School of Integrated Circuits, the Beijing Innovation Center for Future Chip, and the Beijing National Research Center for Information Science and Technology, Tsinghua University, Beijing, China

2. Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA, USA

3. Department of Computer Science, University of California at Santa Barbara, Santa Barbara, CA, USA

Funder

National Key Research and Development Program

NSFC

Beijing S&T Project

Beijing Innovation Center for Future Chip

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9999561/09968289.pdf?arnumber=9968289

Reference25 articles.

1. A 28 nm 64 Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips;si;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2020

2. A 40 nm 4.81 TFLOPS/W 8b floating-point training processor for non-sparse neural networks using shared exponent bias and 24-way fused multiply-add tree;park;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2021

3. A 28 nm 384 kb 6T-SRAM computation-in-memory macro with 8b precision for AI edge chips;su;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2021

4. 15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

5. A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory

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