Approximate Adder Tree Design with Sparsity-Aware Encoding and In-Memory Swapping for SRAM-based Digital Compute-In-Memory Macros
Author:
Affiliation:
1. National Taiwan University,Graduate Institute of Electronics Engineering,Taipei,Taiwan
Funder
National Science and Technology Council
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10595550/10595552/10595967.pdf?arnumber=10595967
Reference10 articles.
1. Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects
2. 16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications
3. DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware
4. An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree
5. An image is worth 16x16 words: Transformers for image recognition at scale;Dosovitskiy,2020
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