An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree-Reference-Cited by-同舟云学术

An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree

Published:2023-02 Issue:2 Volume:70 Page:416-420
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

He Yifan¹,Yue Jinshan²,Feng Xiaoyu¹^ORCID,Huang Yuxuan¹^ORCID,Jia Hongyang¹^ORCID,Wang Jingyu¹^ORCID,Zhang Lu¹,Sun Wenyu³,Yang Huazhong¹^ORCID,Liu Yongpan¹^ORCID

Affiliation:

1. Department of Electronic Engineering, Tsinghua University, Beijing, China

2. Key Laboratory of Microelectronic Devices and Integrated Technology, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China

3. Tsinghua Shenzhen International Graduate School, Shenzhen, China

Funder

National Key Research and Development Program

NSFC

Beijing Nova Program

China Postdoctoral Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10032206/09903897.pdf?arnumber=9903897

Reference18 articles.

1. Ultra high density 3D via RRAM in pure 28nm CMOS process

2. A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm2 using Sneaking Current Suppression and Compensation Techniques

3. Area-efficient embedded RRAM macros with sub-5ns random-read-access-time using logic-process parasitic-BJT-switch (0T1R) cell and read-disturb-free temperature-aware current-mode read scheme;chang;Proc Symp VLSI Technol,2013

4. Study of Drift in RRAM Devices Under Various Operating Conditions

5. Accuracy Optimization With the Framework of Non-Volatile Computing-In-Memory Systems

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