A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS-Reference-Cited by-同舟云学术

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A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS

Published:2024-01 Issue:1 Volume:59 Page:19-28
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Ye Bingyi¹^ORCID,Wu Guangdong¹,Gai Weixin¹^ORCID,Sheng Kai¹^ORCID,He Yandong¹^ORCID

Affiliation:

1. School of Integrated Circuits, Peking University, Beijing, China

Funder

Beijing Major Science and Technology Project

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10375801/10241963.pdf?arnumber=10241963

Reference20 articles.

1. A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET

2. An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS

3. A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels

4. A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET

5. A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Fractionally-Spaced Equalizers as Clock and Data Recovery Loops;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-07

2. Design of X-Band Time Delay Component With High Integration;2023 4th China International SAR Symposium (CISS);2023-12-04

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