An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques-Reference-Cited by-同舟云学术

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques

Published:2021-01 Issue:1 Volume:56 Page:212-224
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Lee Chang-Kyo^ORCID,Chi Hyung-Joon,Heo Jin-Seok,Park Jung-Hwan,Jang Jin-Hun,Lee Dongkeon,Jung Jae-Hoon,Lee Dong-Hun,Kim Dae-Hyun^ORCID,Kim Kihan^ORCID,Kim Sang-Yun,Park Dukha,Lim Youngil^ORCID,Park Geuntae,Lee Seung-Jun,Hong Seungki^ORCID,Kwon Dae-Hyun,Hwang Isak^ORCID,Na Byongwook,Kim Kyung-Ryun,Choi Seouk-Kyu,Choi Hyein,Hangi-Jung ,Bae Won-Il,Ihm Jeong-Don,Bae Seung-Jun,Kim Nam Sung,Lee Jung-Bae

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9306027/09184953.pdf?arnumber=9184953

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