13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction-Reference-Cited by-同舟云学术

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13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction

Published:2024-02-18 Issue: Volume: Page:246-248
ISSN:
Container-title:2024 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Seo Yangho¹,Choi Jihee¹,Cho Sunki¹,Han Hyunwook¹,Kim Wonjong¹,Ryu Gyeongha¹,Ahn Jungil¹,Cho Younga¹,Choi Sungphil¹,Lee Seohee¹,Lee Wooju¹,Lee Chaehyuk¹,Kim Kiup¹,Lee Seongseop¹,Park Sangbeom¹,Choi Minjun¹,Lee Sungwoo¹,Kim Mino¹,Shin Taekyun¹,Jeong Hyeongsoo¹,Kim Hyunseung¹,Song Houk¹,Hong Yunsuk¹,Yoon Seokju¹,Park Giwook¹,You Hokeun¹,Choi Changkyu¹,Jung Hae-Kang¹,Cho Joohwan¹,Kim Jonghwan¹

Affiliation:

1. SK hynix,Icheon,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454381.pdf?arnumber=10454381

Reference3 articles.

1. A 16Gb 9.5 Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process;Kim;ISSCC,2022

2. An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques

3. A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture

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