An ultra-low-power 10-Bit 100-kS/s successive-approximation analog-to-digital converter-Reference-Cited by-同舟云学术

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An ultra-low-power 10-Bit 100-kS/s successive-approximation analog-to-digital converter

Published:2009-05 Issue: Volume: Page:
ISSN:
Container-title:2009 IEEE International Symposium on Circuits and Systems
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Author:

Lotfi Reza,Majidi Rabeeh,Maymandi-Nejad Mohammad,Serdijn Wouter A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5076158/5117665/05117956.pdf?arnumber=5117956

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-02

3. Design and Analysis of a 4-Bit Flash ADC Architecture with Modified Comparator;International Conference on Intelligent Data Communication Technologies and Internet of Things (ICICI) 2018;2018-12-21

4. Analysis design of area efficient segmentation digital to analog converter for ultra-low power successive approximation analog to digital converter;Microelectronics Journal;2016-06

5. A simple structure for noise-shaping SAR ADC in 90nm CMOS technology;AEU - International Journal of Electronics and Communications;2015-08

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