Analysis design of area efficient segmentation digital to analog converter for ultra-low power successive approximation analog to digital converter

Author:

Sharuddin IffaORCID,Lee L.,Yusof Zubaida

Publisher

Elsevier BV

Subject

General Engineering

Reference23 articles.

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3. A low power onsumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array;Kim;IEEE Int. Conf. Electron Devices Solid-State Circuits,2008

4. A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-µm CMOS for medical implant devices;Zhang;IEEE J. Solid-State Circuits,2012

5. R. Lotfi, R. Majidi, M. Maymandi-nejad, W.A. Serdijn, An ultra-low-power 10-Bit 100-kS/s successive-approximation analog-to-digital converter, In: IEEE International Symposium on Circuits and Systems, 2009, pp. 1117–1120, 24–27 May.

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