A simple structure for noise-shaping SAR ADC in 90nm CMOS technology

Author:

Inanlou Reza,Yavari Mohammad

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference28 articles.

1. A 65-nm, 1-A buck converter with multi-function SAR-ADC-Based CCM/PSK digital control loop’;Cliquennois;IEEE J Solid-State Circuits,2012

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3. A very low-power CMOS mixed-signal IC for implantable pacemaker applications;Wong;IEEE J Solid-State Circuits,2004

4. A 10-b 100-kS/s 1-mW general-purpose ADC for cellular telephones;Zamprogno;IEEE Trans Circuits Syst II Express Briefs,2012

5. A 0.5V 1.1MS/sec 6.3fJ/Conversion-Step SAR-ADC with tri-level comparator in 40nm CMOS;Shikata;IEEE J Solid-State Circuits,2012

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3. A Low Power High-Speed 12-Bit SAR ADC using Split Capacitor Based DAC at 45 nm CMOS Technology;2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon);2022-10-16

4. A Third-Order noise-shaping SAR ADC With optimized NTF Zeros for IoT Applications;2022 30th International Conference on Electrical Engineering (ICEE);2022-05-17

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