Author:
Kumar Keshav,Ramkumar K.R.,Kaur Amanpreet,Choudhary Somanshu
Cited by
6 articles.
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1. SSTL IO Standard Based Low Power Design of DES Encryption Algorithm on 28 nm FPGA;2024 IEEE 13th International Conference on Communication Systems and Network Technologies (CSNT);2024-04-06
2. Design of a Power Efficient Model of PWM Generator for Green
Communication using High Performance FPGAs;International Journal of Sensors, Wireless Communications and Control;2024-03
3. Power-Efficient Hardware Design of ECC Algorithm on High Performance FPGA;Mobile Radio Communications and 5G Networks;2023
4. Power-Efficient Secured Hardware Design of AES Algorithm on High Performance FPGA;2022 5th International Conference on Contemporary Computing and Informatics (IC3I);2022-12-14
5. Scalable Implementation of Array of 8-bit-Based RSA With Large Key Size;2022 5th International Conference on Advanced Systems and Emergent Technologies (IC_ASET);2022-03-22