Power-Efficient Hardware Design of ECC Algorithm on High Performance FPGA
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-19-7982-8_31
Reference20 articles.
1. Kumar K, Kaur A, Ramkumar KR, Shrivastava A, Moyal V, Kumar Y (2021) A design of power-efficient AES algorithm on Artix-7 FPGA for green communication. In: 2021 international conference on technological advancements and innovations (ICTAI). IEEE, pp 561–564
2. Kumar K, Ramkumar KR, Kaur A (2020) A lightweight AES algorithm implementation for encrypting voice messages using field programmable gate arrays. Journal of King Saud University-Computer and Information Sciences
3. Kumar K, Ramkumar KR, Kaur A (2020) A design implementation and comparative analysis of advanced encryption standard (AES) algorithm on FPGA. In: 2020 8th international conference on reliability, Infocom Technologies and Optimization (Trends and Future Directions) (ICRITO). IEEE, pp 182–185
4. Kumar K, Ramkumar KR, Kaur A, Choudhary S (2020) A survey on hardware implementation of cryptographic algorithms using field programmable gate array. In: 2020 IEEE 9th international conference on communication systems and network technologies (CSNT). IEEE, pp 189–194
5. Kumar K, Kaur A, Panda SN, Pandey B (2018) Effect of different nano meter technology based FPGA on energy efficient UART design. In: 2018 8th international conference on communication systems and network technologies (CSNT). IEEE, pp 1–4
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