Author:
Kumar Keshav,Kaur Amanpreet,Panda S N,Pandey Bishwajeet
Cited by
11 articles.
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1. SSTL IO Standard Based Low Power Design of DES Encryption Algorithm on 28 nm FPGA;2024 IEEE 13th International Conference on Communication Systems and Network Technologies (CSNT);2024-04-06
2. Design and Analysis of Multi-Protocol Conversion Unit for SPI, I2C and UART;2024 2nd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT);2024-03-15
3. Design of a Power Efficient Model of PWM Generator for Green
Communication using High Performance FPGAs;International Journal of Sensors, Wireless Communications and Control;2024-03
4. Comparative Analysis of Hardware and Software Utilization in the Implementation of Full Adder Using Vivado;2023 7th International Conference On Computing, Communication, Control And Automation (ICCUBEA);2023-08-18
5. Design of an Energy Efficient Serial Communication Device using FPGA;2023 International Conference on Disruptive Technologies (ICDT);2023-05-11