A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/6613639/6629247/06629266.pdf?arnumber=6629266
Cited by 16 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Descriptive Analysis of Different Dual-Port and Single-Port 11T SRAM Cells for Low-Voltage Operations;Lecture Notes in Electrical Engineering;2024
2. Design and Performance Analysis of 11-T SRAM Cell with BTI Reliability;2023 2nd International Conference on Automation, Computing and Renewable Systems (ICACRS);2023-12-11
3. Schmitter trigger-based single-ended stable 7T SRAM cell;Analog Integrated Circuits and Signal Processing;2023-09-23
4. Reliability improved dual driven feedback 10T SRAM bit cell;Microelectronics Reliability;2022-12
5. 67.5-fJ Per Access 1-kb SRAM Using 40-nm Logic CMOS Process;2021 IEEE International Symposium on Circuits and Systems (ISCAS);2021-05
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