Fully Self-Aligned Via Integration for Interconnect Scaling Beyond 3nm Node
Author:
Affiliation:
1. Taiwan Semiconductor Manufacturing Company,Hsinchu,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9720433/9720494/09720600.pdf?arnumber=9720600
Reference10 articles.
1. Self-Correcting Process for High Quality Patterning by Atomic Layer Deposition
2. A New Resist for Area Selective Atomic and Molecular Layer Deposition on Metal–Dielectric Patterns
3. Area-Selective Atomic Layer Deposition Assisted by Self-Assembled Monolayers: A Comparison of Cu, Co, W, and Ru
4. Selective Deposition of Dielectrics: Limits and Advantages of Alkanethiol Blocking Agents on Metal–Dielectric Patterns
5. Mechanism of Precursor Blocking by Acetylacetone Inhibitor Molecules during Area-Selective Atomic Layer Deposition of SiO2
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