Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm-Reference-Cited by-同舟云学术

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Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm

Published:2019-12 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE International Electron Devices Meeting (IEDM)
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Author:

Prasad Divya,Teja Nibhanupudi S. S.,Das Shidhartha,Zografos Odysseas,Chehab Bilal,Sarkar Satadru,Baert Rogier,Robinson Alex,Gupta Anshul,Spessot Alessio,Debacker Peter,Verkest Diederik,Kulkarni Jaydeep,Cline Brian,Sinha Saurabh

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8971803/8993428/08993617.pdf?arnumber=8993617

Cited by 45 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. BS-PDN Implemented the Latest Logic Devices for 14 Angstrom Technology Node;IEEE Transactions on Electron Devices;2024-07

2. Novel Single and Co-Ion Implantation Induced Backside Etch Stop Structures for 3D Multilayer Stacked Package;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

3. Improved RF Performance with Buried Power Rail and Contact over Active Gate in Nanosheet FETs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

4. Reinforcement Learning-Based Optimization of Back-Side Power Delivery Networks in VLSI Design for IR -Drop Reduction;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

5. Backside Interconnects for Power Delivery – Design, Manufacturability & Yield;2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2024-03-03

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