Author:
Parmar Sunil S.,Gharge Anuradha P.
Cited by
8 articles.
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1. Design of a Rail-to-rail 12-Bit 2.5-MSPS SAR ADC with Low-area on 180nm CMOS Process;2024 Tenth International Conference on Communications and Electronics (ICCE);2024-07-31
2. Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications;Engineering Research Express;2024-02-15
3. System dynamics monitoring using PIC micro-controller-based PLSE;Chaos: An Interdisciplinary Journal of Nonlinear Science;2023-07-01
4. An Efficient and Low Power 45nm CMOS Based R-2R DAC;2023 4th International Conference for Emerging Technology (INCET);2023-05-26
5. Generalized Resistive DAC Analysis Through Unitized T-Network Element;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28