An Efficient and Low Power 45nm CMOS Based R-2R DAC
Author:
Affiliation:
1. VNRVJIET,Dept. of ECE,Hyderabad,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10169136/10169900/10170648.pdf?arnumber=10170648
Reference25 articles.
1. An area efficient 10-bit time mode hybrid DAC with current settling error compensation
2. Optimization of capacitive divider for 8-bit DAC realized in 65 nm CMOS process
3. Performance Analysis of RRAM Based Low Power NVSRAM Cell Designs for IoT Applications
4. R-2R ladder circuit design for 32-bit digital-to-analog converter (DAC) with noise analysis and performance parameters
5. A CMOS R-2R ladder digital-to-analog converter and its characterization
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